1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to clock logic in digital circuits.
2. Description of the Related Art
The growing demand for higher performance in devices such as central processing units (CPU) and dynamic random access memories (DRAM) requires faster clocks to drive the circuits in such devices. Synchronizing the operation of different parts of a device can present a major challenge, since the few nanoseconds required to propagate a signal from one circuit to another, or from one part of the integrated circuit to another, may be equivalent to a major part of a single clock cycle. A conventional approach to this dilemma is to generate the different clocks inside the individual circuits, and synchronize those clocks to a reference clock using phase-locked loop (PLL) or delay-locked loop (DLL) circuits.
However, in many cases, it is required that the regenerated clock is not only capable of synchronizing to the reference clock, but is also delayed from that clock by a predetermined amount of time. Simple PLL and DLL circuits are not suited for this because they do not compensate for additional delays that may occur after the synchronized clock signals are produced.